[FPGA/CPLD]8位数据锁存器

mcumao | 当前状态：离线 总积分：1503 2025年可用积分：0 注册时间： 2006-01-20 最后登录时间： 2007-06-11 空间发短消息加为好友: [FPGA/CPLD]8位数据锁存器

mcumao 发表于 2006/4/4 14:11:02 1370 查看 0 回复 [上一主题] [下一主题]

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------------------------------------------------------------------------------------
-- DESCRIPTION   : Flip-flop D type
--                  Width: 8
--                  Clock active: high
--                  Synchronous clear active: high
--                  Synchronous set active: high
--                  Clock enable active: high
--                  Load active: high
------------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity ffd is
port (
CLR : in std_logic;
SET : in std_logic;
CE : in std_logic;
LOAD : in std_logic;
CLK : in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (7 downto 0)
);
end entity;

architecture ffd_arch of ffd is
signal TEMP_DATA_OUT: std_logic_vector (7 downto 0);
begin

process (CLK)
begin

if rising_edge(CLK) then
if CE = '1' then
if CLR = '1' then
TEMP_DATA_OUT <= (others => '0');
elsif SET = '1' then
TEMP_DATA_OUT <= (others => '1');
elsif LOAD = '1' then
TEMP_DATA_OUT <= DATA_IN;
end if;
end if;
end if;

end process;

DATA_OUT <= TEMP_DATA_OUT;

end architecture;

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